Hello, I have an sbRIO board and i want to pass a clock through FPGA from one pin to another. I'm routed a clock to port, say DI (DIO63) and expecting it on another port, say DO (DIO46).
If a use direct connection of one DIO to another in an sctl (all DIOs are configured with 0 synchronization registers for write and read) clock is passing normally and I see it on DO:
Now I want to use a clip for this task. I've created a basic vhdl file:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity user_ip is
port (
clk_in : in std_logic;
clk_out1 : out std_logic
);
end user_ip;
architecture rtl of user_ip is
begin
clk_out1 <= clk_in;
end rtl;
Imported it to project using Component-level IP wizard (see below) with default configs and dropped it do diagram:
<?xml version="1.0" encoding="UTF-8" standalone="no" ?><!-- National Instruments recommends that you do not change this CLIP declaration file outside of the Configure Component-Level IP wizard. You can modify this declaration file on the Component-Level IP page of the FPGA Target Properties dialog box. --><CLIPDeclaration Name="user_ip"><FormatVersion>4.2</FormatVersion><Description/><TopLevelEntityAndArchitecture><SynthesisModel><Entity>user_ip</Entity><Architecture>rtl</Architecture></SynthesisModel><SimulationModel><Entity>user_ip</Entity><Architecture>rtl</Architecture></SimulationModel></TopLevelEntityAndArchitecture><SupportedDeviceFamilies>Unlimited</SupportedDeviceFamilies><InterfaceList><Interface Name="LabVIEW"><InterfaceType>LabVIEW</InterfaceType><SignalList><Signal Name="clk_in"><HDLName>clk_in</HDLName><HDLType>std_logic</HDLType><Direction>ToCLIP</Direction><SignalType>data</SignalType><Description/><DataType><Boolean/></DataType><UseInLabVIEWSingleCycleTimedLoop>Allowed</UseInLabVIEWSingleCycleTimedLoop></Signal><Signal Name="clk_out1"><HDLName>clk_out1</HDLName><HDLType>std_logic</HDLType><Direction>FromCLIP</Direction><SignalType>data</SignalType><Description/><DataType><Boolean/></DataType><UseInLabVIEWSingleCycleTimedLoop>Allowed</UseInLabVIEWSingleCycleTimedLoop></Signal></SignalList></Interface></InterfaceList><ImplementationList><Path Name="user_ip.vhd"><TopLevel/><MD5>dd489bfd1eb7be971758ad462c35b6fc</MD5><SimulationFileList><SimulationModelType>Same as synthesis</SimulationModelType></SimulationFileList> </Path></ImplementationList><NumberOfDCMsNeeded>0</NumberOfDCMsNeeded><NumberOfMMCMsNeeded>0</NumberOfMMCMsNeeded><NumberOfBufGsNeeded>0</NumberOfBufGsNeeded></CLIPDeclaration>
This implementation is running, BUT I do not see any activity on DO (all DIOs are configured with 0 synchronization registers for write and read). What's the problem? What do i need to add/remove/change in a vhdl file and overall clip to make it work?
Konstantin.