I have adopted a lot of LVOOP code on my FPGA designs. The ability to swap out communication channels for inter-loop communication this way is a great feature of LabVIEW FPGA.
I have some questions though.
I am currently assessing the ability to autobalance hetergenous parameter paths with different latencies in my code. All LVOOP code which can return a value is derived from a class which exposes a "Read Latency" dynamic dispatch VI, the content of which is simply a constant wired to the output in the appropriate VI. As the process of FPGA compiling actually removes the "dynamic dispatch" part and essentially inlines the VI call, this code can then be constant folded. If I am careful, I can generate a matrix of delays required for my code to autoadapt to the latencies of the incoming parameter channels. This seems to be working, but i have questions regarding the extent of constant folding going on.
The IDE doesn't seem to want to show me any constant folding at all. But even if it did, I presume it wouldn't have the possibility to display the Dynamic Dispatch calls as beinginlined since this depends on the specific code being injected ar compile time (I could by accident introduce code which can't be folded).
If I were to go about traing to track down what has been optimised away, how would I go about it? I have looked through the Xilinx log for hints regarding the code (by searching for the sub-VI ID string) but don't know what to do with the information.
How much of this constant folding is done by LabVIEW and how much is done by the Xilinx compiler? Even knowing which area to focus my attention on would help a lot.
If the NI Compiler already does constant folding based on the parsing of dynamic dispatch code, should I expect any such code with only static inputs to then not appear in the Xilinx log at all? Would the entire sub-VI be constant folded and never sent to the Xilinx compiler or is it up to the Xilinx compiler to detect and remove static computations? Any help is appreciated.
