I am using LabVIEW 2018 and have a large application that can load and unload SubVIs from multiple subpanel containers. I can start the subVIs and I can shut them down programmatically (not Abort). However I can't seem to find a way to load the subVI in the background so it is running but not visible and then load it into a subpanel when the user is ready to view it. The specific problem I am trying to solve is a Graphs subVI. The Graphs subVI plots a default set of parameters selected by the user (and saved to an ini file) for X amount of time (buffer length). But the graphing doesn't start until the user loads the SubVI into the subpanel container meaning there is no history in the buffer on first call. If I could launch the Graphs.vi in the background during startup then there would be data in the buffer when the user selects that subVI for display in the subpanel. The core problem seems to be that a running vi can't be inserted into a subpanel. Is there a way around this?

Sorry for the confusing subject. I don't really how to put it.

I am working on an assignment for school.
In an XY-graph I need a horizontal line from a numeric controle and a curved line.

I need the intersection point and a way to insert the horizontal line.

The photo is how it is supposed to be. I do have the white line already, with to array's.

Thanks

I'm working on a VI on a Mac and I want to know if it will be possible to open it on Windows Labview and have it run normally. My VI also creates a report through Word and Excel, will that be an issue or should it transfer smoothly to Windows? 

Hi,

I am trying to build a program in Labview in order to acquire the data presented in the waveform of my oscilloscope. I am using a Rigol oscilloscope which is connected to the pc through a usb cable. I am trying to connect the oscilloscope to Labview via Visa. Moreover, the aim of my program is to first present in Labview the waveform depicted in the oscilloscope and secondly to acquire and save the data of the waveform. As I am relatively new to Labview could you please help me build up this program?

Thanks in advance!

Is it correct that a NI USB-8451 can communicate with 8 slaves simultaneously using I2C protocol? Currently, I am using it to communicate with 2 slaves simultaneously. One of these 2 slaves is a TI battery charger EVM and another is a TI fuel gauge. For communication with these, I have to specify the slave address in LabVIEW using the I2C configuration property node. These slave addresses have been provided by TI in their datasheet, and are different for both these devices. So, basically, I'm able to communicate with these 2 slaves simultaneously. 

Now, I want to communicate with four of each of these 2 slaves, i.e. 4 battery chargers and 4 fuel gauges, thus total 8 slaves. Since four of them have the same address, how do I distinguish between them while communication?

P.S.: I'll attach a sample VI of communication with the fuel gauge.

It's a very easy event case.

The problem is that the String to write (hex display) terminal passes the old value rather than the new value to the String out on my boss's computer when I clicked COM Write Button.But the problem never happens on my computer.Our computers' environment both are win7 and LabVIEW2014-Chinese.

Is there anybody can explicate this phenomenon? Thanks.

Hello,

I have spent some time diving through all of the associated shared code, forum discussions, etc. regarding interfacing the Mitutoyo Digimatic Indicator (model 543-392B) via RS-232 and have not been able to properly output the reading. Has anyone had success? My hardware is listed below. I have tried the customized Mitutoyo VIs and the basic serial communication example VIs.

543-392B (Gauge) --> SPC Cable --> IT-007R (RS232 Input Cable) --> TU-S9 (Serial to USB)

Thank you in advance.

Hi LabVIEW community,

Why i am having this type of error?

Hi, 

We have install the NI PXIe-7972R + NI 1483 adapter, and connect to PCO.edge 4.2 camera with camera-link interface. I just follow the user manual (http://www.ni.com/pdf/manuals/375502b.pdf), and use "1-Tap 10-Bit Camera with Frame Trigger.lvproj" switch to our target 7972R FPGA. I can successfully compile the FPGA target as Fig. "troubleshooting_1tap10_1.png". However, when I use the host vi that was not work as Fig. "troubleshooting_1tap10_2.png", it also tell me to recompile. I have already compile many times, it still doesn't work and continuous give the error of FPGA open. I also try the method mentioned in (https://knowledge.ni.com/KnowledgeArticleDetails?id=kA00Z0000019MITSA2&l=zh-TW) as Fig. "troubleshooting_1tap10_3.png", the result is the same, it's still doesn't work. Is there any solution for this condition, thanks?

Best,

Yong

Hi Reader,

I am new to the NI forums, so if my question is not in the best format, please let me know what i should say so that it conforms to forums guidelines.

This might be hard to explain, but I am trying to figure out where the error comes out from here. This code does interface with hardware (a NI USB-6229) and I am running a signal generator and two photodiodes.  In terms of order, I will go from top to bottom, photodiode, photodiode, and signal generator. I assume this would make it difficult for people to actually test this code. So I will do my best to explain what I am doing. 

The middle channel is creating the error.

Essentially, I am trying to turn on two photodiodes and a signal generator simultaneously. I am starting them at the same time, running them hopefully at the same time, and stopping them at the same time. I have ensured that the analog input ports are different for the two photodiodes I am using. I am not entirely sure whether I can use the same clock. If anyone needs more information I am very willing to put up more. 

Note that Main Code is where SO_GetPltrace is located (the sub_VI of the while loop). The error is from SO_GetPLtrace.

Cheers,

Alistrio

Hello,

Could someone please help me how i could plot both output clusters on the same waveform graph?
Please have a look at my VI i attached.

Kind regards,
Balázs

Dear all,

I currently have a setup using a Polytec UHF120 vibrometer system in which I have made a custom LABVIEW program for control of my actuation system and data acquisition. The data is demodulated and I conduct frequency sweep testing which works fine. However, I have to start the vibrometer using the software "Vibsoft" supplied by the company, in which, I turn on the laser for measuring then run my LABVIEW program. This means that the laser is continuously on through out my entire experiment but the samples I am testing are highly reactive to heat due to the laser so I want to be able to turn the laser on/off between test points in order to allow time for a quick measurement say 50 us then if the actuation frequency is the same to turn the laser off say for 2 seconds until a new frequency is detected and the next frequency point is measured. This is a swept sine test so a few seconds between test points is fine just the toggling the laser on/off in labview is my concern.

There are active X controls for the polytec vibrometer, however, I didn't locate one for the laser on/off routine and the company doesn't want to reply how to handle this problem. Has anybody else encountered this problem before or have any ideas? In the Vibsoft software the key command "ctrl+1" will toggle the laser, I am not sure if this could be an alternative way to do this but I am not sure how to send the keys to another software and keep labview as the main program running and only send keys to vibsoft to toggle the laser.

Any help is most appreciated

Kindest regards,

Tanju

hello,

i am new in labview environment and i want to ask how to set alarm for my data (array of 10 hex bytes) so that when a certain value exceeds the limit the alarm starts beeping and color of table changes, in which i am displaying my data on front panel.

and please suggest how to set this alarm on individual byte of hex data.

Hello Community,

I am quite new to LabVIEW, but I have some programming experience with Assembler and C. I am now working on a complex LabVIEW Project for the first time. Now to my Problem:

I want to create a Programm in which the user can choose between multiple functions (SubVI's) and align them in their prefered order for execution. Each function requires the user to enter some variables. The user should also be able to use the same function multiple times with different variables each time.

For example a sequence like this:
1: Function Name: Addition

    Required Variables: A,B

    Set A to 5, Set B to 6

2: Function Name: Delay

    Required Varaibels: T

    Set T to 500ms

3: Function Name: Addition

    Reqired Variables: A, B

    Set A to 6, Set B to 6

.

.

Then the Code would execude in the desired order. Each function that has an Output value that Need to be saved should be collected in a Protocoll which is shown in the end:
1: Sum: 11

2: Sum: 12 

All my functions are working fine on their own. The creation of a fixed sequence is also not a Problem. It would be nice if someone has an idea how to create such an interface and can Point me in the Right direction to do so.

Any help is highly appreciated. Thank you very much!

Hi,
I have stuck with my program.. I have uff file with vibration data. In this file I have data in m/s^2(t) units. And i want to do a 1/3 octave analize on it, so I would like to have on x axis from 0,5 Hz to 100 Hz and on y axis value in m/s^2. How can i do it, with setting proper reference value from my recorder. So in other words I don't want to have dB/Hz but( m/s^2)/Hz.

I have tried understanding and working on one of the built-in examples in LabVIEW NXG which is also discussed in githun as shown in the  link below:
https://github.com/ni/webvi-examples/tree/master/CallLabVIEWWebService

The first issue, I faced was to communicate LabVIEW NXG 2.1 and Standard LabVIEW 2018. The issue was due to using two different ports i.e. 8080 for debug port in LabVIEW 2018 and port 8001 in LabVIEW NXG 2.1. It was throwing an error of CORS origin or the client was not able to reach the target server. Finally I solved the issue by using an unsed port say 5007 for both the applications and it worked fine! Also I am able to build and run the web application in any browser in my local PC.
Now I am facing two issues here:

1. I have followed the 'Setup' steps as mentioned in the example in GitHub.
   If I run the Main.gviweb in NXG and then go to WebApp.gcomp and build it. The build fails by giving a error with the message 'dependency is currently running'. Then, I am not able to access the web application in the web.
   However, once i run the Main.gviweb and stop it. After halting it's execution and then trying to build it, this time it works.
   Can someone tell me why this happens? Why can't I run the gviweb and then build?Why should i first stop ist execution and then build it?

2. I want to host the web application in a remote system connected with the same network as the local PC (where the LabVIEW webservice is running). I have tried with the follwing url, but I am not able to access it remotely:
   http://lPaddress_of_local_PC/WebApp_Web%20Server/Main.html

Can someone tell how I can acccess the link from any remote Sysem?

Does anyone know if it is possible to do parallel execution between LV NXG and Standard LV? Since the example  executes in a serial manner i.e. NXG sents the data in JSON format to standard LV and once all the procesing is completed in Standard LV then it sends the output in JSON format back to the NXG progran. What if all These Things can be done parallely?

PS: If anyone has more detailed information or materials about LabVIEW NXG with be of great help!Thank you

Hi,

Is there another way of authenticating a user rather than using "runas" command when calling "System exe" within LabVIEW? By authenticating, I mean, checking if a user typed valid windows login password.

When calling "runas", an application to be run needs to be specified. Therefore, there would be another application appearing upon successful password. However, the intention is to check the password only and not to open another app.I wonder is there another way of doing this? Is there a pre-developed LabVIEW library?

Thanks in advance

Hello everyone, 

I'm trying to import a .vhd file (VHDL code) to Labview FPGA as CLIP. But it seems to have a syntax error near code "package body". In this code, package body is empty, but that is not always necessary. Can it cause a problem in this code?

In addition, Labview says that it support only VHDL1993 or VHDL2002 syntax. Is that possible a VHDL version problem? I'm total new to VHDL and have attached the error information and the VHDL code. Anyone know where is the problem?

Any help will be appreciated.

Here is the error information:

Extracting top-level synthesis file information. Please wait...
Processing files...
Processing files...
Vivado Simulator 2017.2
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
Running: C:/NIFPGA/programs/Vivado2017_2/bin/unwrapped/win64.o/xelab.exe xil_defaultlib.conf058585D94A9B43218EA7A6E85ADDCEB1 -L xil_defaultlib -L unisim -L unimacro -L xilinxcorelib -L secureip -snapshot timetag_core_pkg -dll -prj clipsyn.prj
Multi-threading is on. Using 2 slave threads.
Determining compilation order of HDL files.
INFO: [VRFC 10-163] Analyzing VHDL file "C:/NIFPGA/iptemp/clipFC59D81E156944CAB7E0007607C44190/timetag_core_pkg.vhd" into library xil_defaultlib
Vivado Simulator 2017.2
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
Running: C:/NIFPGA/programs/Vivado2017_2/bin/unwrapped/win64.o/xelab.exe xil_defaultlib.conf058585D94A9B43218EA7A6E85ADDCEB1 -L xil_defaultlib -L unisim -L unimacro -L xilinxcorelib -L secureip -snapshot timetag_core_pkg -dll -prj clipsyn.prj
Multi-threading is on. Using 2 slave threads.
Determining compilation order of HDL files.
INFO: [VRFC 10-163] Analyzing VHDL file "C:/NIFPGA/iptemp/clipFC59D81E156944CAB7E0007607C44190/timetag_core_pkg.vhd" into library xil_defaultlib
ERROR: [VRFC 10-1412] syntax error near is [C:\NIFPGA\iptemp\clipFC59D81E156944CAB7E0007607C44190\timetag_core_pkg.vhd:96]
INFO: [VRFC 10-240] VHDL file C:/NIFPGA/iptemp/clipFC59D81E156944CAB7E0007607C44190/timetag_core_pkg.vhd ignored due to errors

Fix the above error and check syntax again.

--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Timetag core package
-- http://www.ohwr.org/projects/fmc-adc-100m14b4cha
--------------------------------------------------------------------------------
--
-- unit name: timetag_core_pkg.vhd (timetag_core_pkg.vhd)
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 05-07-2013
--
-- version: 1.0
--
-- description: Package for timetag core
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see svn log.
--------------------------------------------------------------------------------
-- TODO: - 
--------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;

package timetag_core_pkg is

  ------------------------------------------------------------------------------
  -- Constants declaration
  ------------------------------------------------------------------------------

  ------------------------------------------------------------------------------
  -- Types declaration
  ------------------------------------------------------------------------------
  type t_timetag is record
    meta : std_logic_vector(31 downto 0);
    seconds : std_logic_vector(31 downto 0);
    coarse : std_logic_vector(31 downto 0);
    fine : std_logic_vector(31 downto 0);
  end record t_timetag;

  ------------------------------------------------------------------------------
  -- Components declaration
  ------------------------------------------------------------------------------
  component timetag_core
  port (
    -- Clock, reset
    clk_i   : in std_logic;             -- Must be 125MHz
    rst_n_i : in std_logic;

    -- Input pulses to time-tag
    trigger_p_i   : in std_logic;
    acq_start_p_i : in std_logic;
    acq_stop_p_i  : in std_logic;
    acq_end_p_i   : in std_logic;

    -- Trigger time-tag output
    trig_tag_o : out t_timetag;

    -- Wishbone interface
    wb_adr_i : in  std_logic_vector(4 downto 0);
    wb_dat_i : in  std_logic_vector(31 downto 0);
    wb_dat_o : out std_logic_vector(31 downto 0);
    wb_cyc_i : in  std_logic;
    wb_sel_i : in  std_logic_vector(3 downto 0);
    wb_stb_i : in  std_logic;
    wb_we_i  : in  std_logic;
    wb_ack_o : out std_logic
    );
end component timetag_core;


end timetag_core_pkg;

package body timetag_core_pkg is



end timetag_core_pkg;

I'm starting my first few pieces of work with a Kintex 7 FPGa target and have some questions about Vivado compile times.

I wanted to make a simply test VI which utilises a lot of BRAM, LUT, Register and DSP.  I have a lop-level loop with 192 instances of a simple sub-VI (1x BRAM Read / Write, 1x DSP multiply and a few feedback nodes).  Really nothing complicated.  My problem is that just the "Generating Xilinx IP" takes upwards of 6 hours.  It ocmpiled eventually, but a local compile was over 2x as fast as a cloud compile.  Is this representative for other compiles?

I also tried compiling an instance where I had 3x the top-level loop (3x192 isntances of sub.VI and 3x FP controls) - this should put my Register usage at approx. 60% and LUT also. BRAM around 80% and DSP 90%.  Probably won't compile, but whatever. This compiled for 24 hours, didn't get out of the Generating IP stage and then cancelled the compilation ebcause communication with the compile server broke.  I now have two compiles running in Cloud compile blocking two instances of my 5 licenced compiles.  I have no idea how long they will take.  I can't reconnect to them and I can't cancel the compiles.

I'm wary that this might somehow be a taste of things to come.

Hi!

We have several computers, and each is used to develop a common project. SVN is used as version control, and everything works fine, so far.

The project has one base class with many child classes, and while child classes are added an modified often, the base class itself has not been touched for a long time, now.

But.. there is a single method VI in the base class which claims to be modified as soon as someone pulls an SVN update and starts developing, and when this VI comes from another computer. After the next commit and update on an other computer, LabVIEW will change it there, again.

The point is: We did not change (nor open) this VI. We even separated compiled code from the VI to overcome minor differences in compiled code.

LabVIEW says that a break point was set or cleared, and indeed the VI contains a single break point, which is used as assertion in case of unexpected data. But other VIs also have break point, and don't show this problem. This is also why I can't provide a sample, since it only happens with this one VI.

Any idea what could be the reason?