Hi all,
I am using an FPGA (7965R with 5761 digitiser front module) to do some real time data analysis. I want to use all four channels of the digitiser and use DMA FIFOs to send four streams of data for each channel. 4x4=16 DMA FIFOs which squeaks in just under the limit of 16 available DMA FIFOs on this FPGA/chassis. I want to do all this programatically, using actors, on the RT.
I am using Advanced Session Resources (ASR) to pull out specific FIFOs from the the FGPA reference. I then use FIFO reads in parallel FIFO listener loops to read the FIFOs. My problem is that I quickly receive a -63198 error, which I have deduced is because I am trying to open too many FPGA references. Does the 'cast' in ASR result in the creation of a new reference? I will assume from here that it does...
I read that there is a hard limit of 16 open FPGA references. Since I have 16 already from just the dynamic reads of 16 FIFOs, and I will have a few more when created when I initialise the system and go about creating the dynamic references, I suspect my error is caused by hitting this limit.
Now, solutions:
I could create each reference immediately before the read and close it right after, but I have read that this would add a lot of overhead to my reads! Not ideal for code that I want to operate ASAP. My host PC also has a FPGA reference for sending settings direct to the FPGA, in this case I could manage with opening and closing the reference each time, since I don't need the response to be deteministic or fast.
My only solution so far is to squeeze all four data streams for each channel into a single DMA FIFO. Then create a single reference for each using ASR. I would need a parent reference to create these on the RT. Then I would need one for the host which I would create/destroy as necessary. This adds up to 6 simultaneous references, which should be acceptable.
Can anyone think of a better way to do programatic referencing of DMA FIFOs? Perferably one that doesn't result in the creation of so many references. Please bear in mind that I really want to maintain the dynamic design of the application, to maximise the resue of the FIFO listening actors.