I am using NI PXIe-1062Q Chasis (connected to a Dell workstation Precision 1700) with the following modules :
1. NI PXIe-8381
2. NI PXI 7851 R
3. NI PXIe-6738
4. NI PXIe-6535
In my workstation, I have plugged in the PCIe-8381 module for connecting NI PXIe-8381 to the computer into a PCI-E Gen 3 x16 slot. I want to execute a sequence of operations from NI PXI 7851 R FPGA card using an FPGA VI controlled from a Non-FPGA Host VI. For this, I write the operations inside a case structure in my FPGA VI. The user will give the sequence of operations by simply typing the array of numeric values corresponding to various operations of the case structure in the order he/she wants. This array is transferred from the Host to FPGA VI by a DMA FIFO. Now here is my question :
Q.1. Suppose I have an FPGA Wait function (with a control value passed from Host VI) as a particular case of the case structure in FPGA VI. I want the user to be able to specify different control values for the same Wait function case of the FPGA VI i.e. suppose the wait function case is no. "2". So In my FIFO whenever I say "2" I should also tell the control value for this particular occurrence of the "case 2". Next time when again "2" occurs in the FIFO it will have its own control value which might be different from that of earlier "2". Is there a simple way of passing the control values each time the particular case is called from the Host? Right now I can specify one wait time control value in the Host which passes to FPGA VI say 1 μs. If I want to wait for 100 μs I have to type "2" 100 times in FIFO. But this is not user-friendly and might not be a solution always. Here it works because time simply adds.
This method would help when I scale the FPGA VI later adding several cases some of which might have control values coming from Host. Whenever the Host calls these particular cases, it should also tell all the control values required by a particular case for this single occurrence. Later on, if this case is called again in the FIFO, a fresh set of control values will be supplied by the Host VI.
I am attaching my Host and FPGA VIs and their screen-shots. I tried to switch ON a TTL signal in one channel of Connector 0 of 7851R. After some wait time (1 μs), I switch off the TTL signal in the channel (FIFO array sequence from the host is: 1,2,3). I see a nice TTL pulse on my oscilloscope but the above issue remains to be resolved.![Top_level_Non_FPGA_VI_using_FPGA_FIFO_VI]( "Top_level_Non_FPGA_VI_using_FPGA_FIFO_VI.JPG")
Top_level_Non_FPGA_VI_using_FPGA_FIFO_VI
![FPGA_VI_using_FIFO]( "FPGA_VI_using_FIFO.JPG")
FPGA_VI_using_FIFO
