FPGA Loop Timer Runs Unchecked When Executing on Development Computer

Hello forum,

I am developing FPGA code, and I am running and debugging with the Execute VI on > Development Computer with Simulated I/O option. However, I have noticed that my Loop Timer VIs do not seem to be timing my loops. The loops run unchecked as if they have no timing in them at all. This is how I implement it:

1. I place the Loop Timer VIs within a Conditional Disable Structure with FPGA_EMULATION==TRUE.
2. That Conditional Disable Structure is in the first frame of a Flat Sequence Structure.
3. This is all in a While Loop

I can create a blank VI from a blank project and have the same results. My understanding is that when a Loop Timer VI executes on the Development Computer, it automatically rounds to ms since Windows only has 1 ms resolution. But even if I choose mSec as the Counter units and wire in 1000 or 10000 I get the same results. From using the blank VI and 10000 mSec wired in, I know that my code is not taking longer than the Timer duration, so it should not return immediately.

I feel like I am just missing something simple, but have not been able to find any reference to this issue in the forums or through searching elsewhere.

Thank you for your help,

W