FPGA Parallel IO Speed

Hi,

I'm trying to read and write to several FPGA analog IO's in parallel.

I'm using a cRIO 9076 and a NI9467 & NI9205 for the outputs and inputs respectively.

The problem i'm facing is that i need to sample each of the inputs and write to all the outputs every 50usec.

With the hardware that i'm using now, the fastest i can achieve is about 120usec.

Also, to simplify the coding process, i'm using FIFO's for data transfer between the RT host VI and the FPGA VI (instead of interrupts). I'm also RT VI directly on a host computer (i don't have another VI to communicate with the RT VI).

Could any of these be the problem?

I can upload the code if anyone would want to take a look.

Thanks!