Synchronizing DMA FIFO Buffers

Hi All,

I am attempting to transfer four channels of data (each channel is 32 bits) from an FPGA target to a host. I'm stuffing two channels each into a DMA FIFO buffer, so I have two DMA buffers.

The samples need to be synchronized in time, so data pulled off the two DMA buffers need to be synchronized. I have read many posts with people in similar circumstances, no solutions of which work when the total number of bits to be synchronized exceeds 64.

Is there a clever way to guarantee synchronization of two 64-bit FIFO DMA buffers between an FPGA and windows host?