While updating FPGA VIs from LV 2017 to LV 2019 for my customers' multi-year projects, I have run into a trouble in that LV FPGA WDP FFT IP consumes much larger amount of Block RAM in Vivado 2017.02 than it does in Vivado 2015.04, for exact the same settings.
The setting is as shown in the picture below.
- FFT Length: 65536
- Input Data: 2 Samples Per Cycle (signed,18, 18 FXP)
- Goal: Accuracy
- Clock Rate: 128MHz
Just placing the WDP FFT with the above settings and connected its input and output, the FPGA VI is compiled on LabVIEW 2017 (Vivado 2015.4) and LabVIEW 2019 (Vivado 2017.2). FPGA is xc7k410t (Hardware is NI-7935R) The compilation results are as shown below.
On LV 2017 (Vivado 2015.4), total amount of Block RAM used is 540 out of 795 (67.9%).
On LV 2019 (Vivado 2017.2), total amount of Block RAM used is 668 out of 795 (84.0%).
This is a significant increase in Block RAM usage for the same design. This increase of Block RAM usage for WDP FFT leads top-level design to shortage in Block RAM, and FPGA VIs generate compilation errors on LabVIEW 2019.
Is this something officially recognized by NI? Regardless it is or not, is there any workaround for this circumstance? I have multiple customers's projects where WDP FFTs are used. The amount of increase in BRAM usage for WDP FFT is significant and cannot be ignored for most of the users of WDP FFT.
I come up with some relatively easy workarounds for this situation, such as
- use bitfile compiled on 2017 for 2019
- use multiple instances of Xilinx LogiCore FFT IP and make them work in parallel
but ideally WDP FFT should consume the same amount of Block RAM both versions in Vivado compilation tool.
Please help us.
Osamu Fujioka
TRIONIX Inc.
CLED/CLA
LabVIEW FPGA and Software Designed Instrument Expert