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7966R - DSTARA Clock and AT-1120

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What is the reason for the DSTARA clock being 124.98 MHz on the 7966R, but 125 MHz on all other similar FlexRIO devices. 

 

Also if anyone has used the AT-1120, can the SCTL in the FPGA VI for sending data to the CLIP inputs on the 16 channels for output, be anythnig other than the 125 MHz I/O module clock? That is can the effective rate of this digitizer be reduced to achieve other sampling rates? 

 

Thanks for your help. 


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