Type of the source is void while importing external IP

Absolute beginer (about ~10 hours in) trying to instantiate an external VHDL IP on a FPGA target. I followed this technical note up to the point where I tried to connect an output port of the IP to a led. Connecting both always trigger the same error: The type of the source is void. I believe that the port is defined properly in the CLIP:

<Signal Name="outLed">

   <HDLName>outLed</HDLName>

   <Datatype>

      <Boolean/>

   </Datatype>

   <Direction>FromCLIP</Direction>

   <SignalType>data</SignalType>

</Signal>

Which I believe matches the VHDL entity:

entity IPNode is

port(

    ap_clk :INSTD_LOGIC;

    ap_rst :INSTD_LOGIC;

    ap_start :INSTD_LOGIC;

    ap_done :OUTSTD_LOGIC;

    ap_idle :OUTSTD_LOGIC;

    ap_ready :OUTSTD_LOGIC;

    outLed :OUTSTD_LOGIC);

end;

For the record I use Labview 2013 and I'm targeting the Zynq Z010 on a MyRIO.