Single Cycle Time Loop

Hi

I wrote two FPGA programs one with SCTL and one without SCTL. Both of these programs are the same(except in using SCTL). The result is strange for me. The first Program(with SCTL) uses very low of resources:

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(Total Slices : 4.5% , Slice Registers: 1.2% , Slice LUTs :2.6% , DSP48s: 1.7%)

While the resources which the other program uses are very higher than the first one :

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(Total Slices : 38% , Slice Registers: 18.2% , Slice LUTs :26.5% , DSP48s: 27.6%)

I want to know, is this huge difference, normal? 

Thanks