I have an application where I am comparing limits to the input values from two strain cards (NI-9237) inside an FPGA which is doing some signal conditioning for a sub-system in a larger machine.
Process limits are sent from the RT as an array and compared against an input array of "raw" data-
Input Data-
Limit Comparison-
I am doing a by element to "OR array" and I realize that this may or may not be more effiecient as a compare aggregates; however, the strange thing that is happening is that the sixth element in the limit array is triggering a "Load Error" for the fifth element in the input array.
I am sending the limit directly from the FP of the RT-
Notice that the calculation checked by reading back the value that was set in the FPGA. This set and get seem to line up here. IE, if you set element 3 in either MaxLoad% or LCNominal(mV/V), it is validated on the FPGAMaxLoad output. I am wondering if this has anything to do with the implicit conversion between single floating point to fixed point?
If anyone else has experienced this, I would appreciate the feedback on what is happening.
I really don't want to go down the DMA route since this is a very small array of six elements an it seems over kill to use up a DMA channel just for this operation.
Thanks,
Drew