Hello all,
I am trying to run my first FPGA project using a myRIO and SPI protocol from an ADC. I am only concerned with reading data from the ADC. I found this link that was posted a few years back with a modified program for myRIO.
https://forums.ni.com/t5/Labvolution/myRIO-FPGA-SPI-Communications/ba-p/3484859
I have slightly modified the project to accommodate the pins that I will be using. I have also created a master clock (MCLK) used to send to the ADC to control sampling rate. This is executing just fine. My issue is that I am not generating the SCLK that is needed in order to read/write data for SPI. I know I can configure in the cluster from the front panel of the RT host or the FPGA top level. I am just not seeing anything except noise on my o-scope. I am not getting any errors when compiling the program and my hardware is wired correctly. I am stumped after trying to figure out what I am missing. Could somebody please take a look at this and see if I have made a small error somewhere? Any help will be greatly appreciated.
Thanks