top level clock timing error 0.00 ns

I am working with Ni 9146 chassis in FPGA.  When the top-level clock was set to default (40 MHz) and the VI was compiled with Xilinx a timing error comes back which states the the time that the code took would be ~0.05 ns, but the expected time was 0.00ns.  Since it was 40 MHz the time required should have been 25ns.  I had the work around that I created a derived clock of 40 MHz, and this makes the compiler think the code needs to run in less than 25ns.  

I do need to know why the default clock does not work though.  

Thank you for your time

Mitchell