Hi
Just reporting a problem I made for myself, where the LabVIEW IDE would allow me start FPGA compilation, but the Xilinx compiler would return an error.
I had created a FOR loop with 2 auto-indexed input arrays. One was a fixed length - no problem. The other was an output array from the FOR loop looped back through a feedback node as an input to the same FOR loop. Inspecting the wire it was not of fixed length. From the Xilinx error message, I think the array was being used before being instantiated - no default value.
The error had the phrase "formal <array_in> has no actual or default value".
The solution was to explicitly index the second array inside the FOR loop with 'index array'. Defining the number of iterations of the FOR may also have worked, and would save on FPGA resources.
Hopefully this helps someone in the future,
Cheers