USB-8451 Inter-Byte Setup Delay

Greetings,

I'm working with an FPGA that has registers programmed VIA SPI.

I've attached a snapshot of a 3-byte packet that's correct, but has some features that I would like to adjust if possible.

First, the top data is Chip Select, the middle data is the data bytes (MOSI), and the bottom is the clock data. Please disregard the names (Anode, Cathode, etc., as this is from a prior measurement)

The delay between byes (called the setup delay in SPI parlance), can it be adjusted, or is this fixed?

The MOSI data defaults to high state when not writing data. I know the clock can be set to "idle high" or "idle low", but can the MOSI also be set similarly, in which case I'd like for it to be low before data, during the setup time, and after data.

I don't have HSDIO board to use, so I'm stuck with the USB device at the moment.

Thanks in advance,

TR